1. Field of the Invention
The present invention relates to a Group III nitride semiconductor device, and to a method for producing the device. More particularly, the present invention relates to a semiconductor device with reduced on-state resistance (e.g., an HEMT (high electron mobility transistor), also called an HFET (heterostructure field effect transistor), the term of HEMT is used in the present specification, or a diode), and to a method for producing the device. The present invention also relates to a power converter including such a Group III nitride semiconductor device.
2. Background Art
Group III nitride semiconductors have been widely used as a material for light-emitting devices. Also, Group III nitride semiconductors are envisaged as a material for power devices, since they exhibit high electron mobility and have a breakdown field strength about 10 times that of Si. Hitherto developed power devices include an HEMT (high electron mobility transistor) in which a two-dimensional electron gas (2DEG) layer formed at a heterojunction interface serves a channel. When a GaN HEMT is produced so as to have the same structure as a conventional HEMT (e.g., GaAs HEMT), the GaN HEMT exhibits a normally-on characteristic; i.e., the HEMT is in an ON state under application of no voltage to a gate electrode. However, an HEMT exhibiting a normally-on characteristic poses a safety problem. Therefore, there have been proposed various HEMT structures which realize a normally-off characteristic (i.e., no current flows between a source electrode and a drain electrode under application of no voltage to a gate electrode).
For example, Japanese Patent Application Laid-Open (kokai) No. 2008-147593 discloses an HEMT which realizes a normally-off characteristic; specifically, an HEMT having an MIS structure in which a carrier supply layer is not formed directly below a gate electrode. This structure realizes a normally-off characteristic, since a 2DEG layer is not formed in a region directly below the gate electrode. In order to achieve this structure, Japanese Patent Application Laid-Open (kokai) No. 2008-147593 discloses a method for exposing a surface of a carrier transport layer by removing a portion of a carrier supply layer through dry etching.
Japanese Patent Application Laid-Open (kokai) No. 2009-99691 discloses a method for producing an HEMT, in which a first carrier supply layer is formed on a carrier transport layer; a mask is formed on a specific region of the first carrier supply layer; two second carrier supply layers are formed, through selective re-growth, on unmasked regions of the first carrier supply layer so that the second carrier supply layers are separated from each other; a source electrode is formed on one of the second carrier supply layers; a drain electrode is formed on the other second carrier supply layer; and a gate electrode is formed on the mask.
However, when the structure disclosed in Japanese Patent Application Laid-Open (kokai) No. 2008-147593 is produced through the method using selective re-growth disclosed in Japanese Patent Application Laid-Open (kokai) No. 2009-99691, problems arise in that, for example, impurities, etc. are incorporated at the interface between a carrier transport layer and a carrier supply layer when the carrier supply layer is grown on the carrier transport layer, and flatness of the interface between these layers is degraded, which results in reduction in mobility of 2DEG generated at the heterojunction interface between the carrier transport layer and the carrier supply layer, and an increase in on-state resistance.